Machinekit Documentation

HAL Component — SIM_PARPORT

INSTANTIABLE COMPONENTS — General

All instantiable components can be loaded in two manners

Using loadrt with or without count= | names= parameters as per legacy components
Using newinst, which names the instance and allows further parameters and arguments
primarily pincount= which can set the number of pins created for that instance (where applicable)

NAME

sim_parport — A component to simulate the pins of the hal_parport component

SYNOPSIS

sim_parport

USAGE SYNOPSIS

loadrt sim_parport
OR
newinst sim_parport <newinstname> [ pincount=N | iprefix=prefix ] [instanceparamX=X | argX=X ]

( args in [ ] denote possible args and parameters, may not be used in all components )

DESCRIPTION

Sim_parport is used to replace the pins of a real parport without changing any of the pins names in the rest of the config. .br It has pass-through pins (ending in -fake) that allows connecting to other components.

eg pin-02-in will follow pin-02-in-fake 's logic. .br pin_01_out-fake will follow pin_01_out (possibly modified by pin_01_out-invert)

It creates all possible pins of both 'in' and 'out' options of the hal_parport component. .br This allows using other hardware I/O in place of the parport (without having to change the rest of the config) .br or simulating hardware such as limit switches. .br it’s primary use is in Stepconf for building simulated configs. .br You must use the names= option to have the right pin names. .br eg. names=parport.0,parport.1 .br The read and write functions pass the logic from pins to fake pins or vice vera .br The reset function is a no operation.

FUNCTIONS

sim_parport.N.read.funct ( OR <newinstname>.read.funct )

sim_parport.N.write.funct ( OR <newinstname>.write.funct )

sim_parport.N.reset.funct ( OR <newinstname>.reset.funct )

PINS

sim_parport.N.pin-01-out bit in ( OR <newinstname>.pin-01-out bit in )

sim_parport.N.pin-02-out bit in ( OR <newinstname>.pin-02-out bit in )

sim_parport.N.pin-03-out bit in ( OR <newinstname>.pin-03-out bit in )

sim_parport.N.pin-04-out bit in ( OR <newinstname>.pin-04-out bit in )

sim_parport.N.pin-05-out bit in ( OR <newinstname>.pin-05-out bit in )

sim_parport.N.pin-06-out bit in ( OR <newinstname>.pin-06-out bit in )

sim_parport.N.pin-07-out bit in ( OR <newinstname>.pin-07-out bit in )

sim_parport.N.pin-08-out bit in ( OR <newinstname>.pin-08-out bit in )

sim_parport.N.pin-09-out bit in ( OR <newinstname>.pin-09-out bit in )

sim_parport.N.pin-14-out bit in ( OR <newinstname>.pin-14-out bit in )

sim_parport.N.pin-16-out bit in ( OR <newinstname>.pin-16-out bit in )

sim_parport.N.pin-17-out bit in ( OR <newinstname>.pin-17-out bit in )

sim_parport.N.pin-01-out-fake bit out ( OR <newinstname>.pin-01-out-fake bit out )

sim_parport.N.pin-02-out-fake bit out ( OR <newinstname>.pin-02-out-fake bit out )

sim_parport.N.pin-03-out-fake bit out ( OR <newinstname>.pin-03-out-fake bit out )

sim_parport.N.pin-04-out-fake bit out ( OR <newinstname>.pin-04-out-fake bit out )

sim_parport.N.pin-05-out-fake bit out ( OR <newinstname>.pin-05-out-fake bit out )

sim_parport.N.pin-06-out-fake bit out ( OR <newinstname>.pin-06-out-fake bit out )

sim_parport.N.pin-07-out-fake bit out ( OR <newinstname>.pin-07-out-fake bit out )

sim_parport.N.pin-08-out-fake bit out ( OR <newinstname>.pin-08-out-fake bit out )

sim_parport.N.pin-09-out-fake bit out ( OR <newinstname>.pin-09-out-fake bit out )

sim_parport.N.pin-14-out-fake bit out ( OR <newinstname>.pin-14-out-fake bit out )

sim_parport.N.pin-16-out-fake bit out ( OR <newinstname>.pin-16-out-fake bit out )

sim_parport.N.pin-17-out-fake bit out ( OR <newinstname>.pin-17-out-fake bit out )

sim_parport.N.pin-01-out-invert bit io ( OR <newinstname>.pin-01-out-invert bit io )

sim_parport.N.pin-02-out-invert bit io ( OR <newinstname>.pin-02-out-invert bit io )

sim_parport.N.pin-03-out-invert bit io ( OR <newinstname>.pin-03-out-invert bit io )

sim_parport.N.pin-04-out-invert bit io ( OR <newinstname>.pin-04-out-invert bit io )

sim_parport.N.pin-05-out-invert bit io ( OR <newinstname>.pin-05-out-invert bit io )

sim_parport.N.pin-06-out-invert bit io ( OR <newinstname>.pin-06-out-invert bit io )

sim_parport.N.pin-07-out-invert bit io ( OR <newinstname>.pin-07-out-invert bit io )

sim_parport.N.pin-08-out-invert bit io ( OR <newinstname>.pin-08-out-invert bit io )

sim_parport.N.pin-09-out-invert bit io ( OR <newinstname>.pin-09-out-invert bit io )

sim_parport.N.pin-14-out-invert bit io ( OR <newinstname>.pin-14-out-invert bit io )

sim_parport.N.pin-16-out-invert bit io ( OR <newinstname>.pin-16-out-invert bit io )

sim_parport.N.pin-17-out-invert bit io ( OR <newinstname>.pin-17-out-invert bit io )

sim_parport.N.pin-01-out-reset bit io ( OR <newinstname>.pin-01-out-reset bit io )

sim_parport.N.pin-02-out-reset bit io ( OR <newinstname>.pin-02-out-reset bit io )

sim_parport.N.pin-03-out-reset bit io ( OR <newinstname>.pin-03-out-reset bit io )

sim_parport.N.pin-04-out-reset bit io ( OR <newinstname>.pin-04-out-reset bit io )

sim_parport.N.pin-05-out-reset bit io ( OR <newinstname>.pin-05-out-reset bit io )

sim_parport.N.pin-06-out-reset bit io ( OR <newinstname>.pin-06-out-reset bit io )

sim_parport.N.pin-07-out-reset bit io ( OR <newinstname>.pin-07-out-reset bit io )

sim_parport.N.pin-08-out-reset bit io ( OR <newinstname>.pin-08-out-reset bit io )

sim_parport.N.pin-09-out-reset bit io ( OR <newinstname>.pin-09-out-reset bit io )

sim_parport.N.pin-14-out-reset bit io ( OR <newinstname>.pin-14-out-reset bit io )

sim_parport.N.pin-16-out-reset bit io ( OR <newinstname>.pin-16-out-reset bit io )

sim_parport.N.pin-17-out-reset bit io ( OR <newinstname>.pin-17-out-reset bit io )

sim_parport.N.pin-02-in bit out ( OR <newinstname>.pin-02-in bit out )

sim_parport.N.pin-03-in bit out ( OR <newinstname>.pin-03-in bit out )

sim_parport.N.pin-04-in bit out ( OR <newinstname>.pin-04-in bit out )

sim_parport.N.pin-05-in bit out ( OR <newinstname>.pin-05-in bit out )

sim_parport.N.pin-06-in bit out ( OR <newinstname>.pin-06-in bit out )

sim_parport.N.pin-07-in bit out ( OR <newinstname>.pin-07-in bit out )

sim_parport.N.pin-08-in bit out ( OR <newinstname>.pin-08-in bit out )

sim_parport.N.pin-09-in bit out ( OR <newinstname>.pin-09-in bit out )

sim_parport.N.pin-10-in bit out ( OR <newinstname>.pin-10-in bit out )

sim_parport.N.pin-11-in bit out ( OR <newinstname>.pin-11-in bit out )

sim_parport.N.pin-12-in bit out ( OR <newinstname>.pin-12-in bit out )

sim_parport.N.pin-13-in bit out ( OR <newinstname>.pin-13-in bit out )

sim_parport.N.pin-15-in bit out ( OR <newinstname>.pin-15-in bit out )

sim_parport.N.pin-02-in-fake bit in ( OR <newinstname>.pin-02-in-fake bit in )

sim_parport.N.pin-03-in-fake bit in ( OR <newinstname>.pin-03-in-fake bit in )

sim_parport.N.pin-04-in-fake bit in ( OR <newinstname>.pin-04-in-fake bit in )

sim_parport.N.pin-05-in-fake bit in ( OR <newinstname>.pin-05-in-fake bit in )

sim_parport.N.pin-06-in-fake bit in ( OR <newinstname>.pin-06-in-fake bit in )

sim_parport.N.pin-07-in-fake bit in ( OR <newinstname>.pin-07-in-fake bit in )

sim_parport.N.pin-08-in-fake bit in ( OR <newinstname>.pin-08-in-fake bit in )

sim_parport.N.pin-09-in-fake bit in ( OR <newinstname>.pin-09-in-fake bit in )

sim_parport.N.pin-10-in-fake bit in ( OR <newinstname>.pin-10-in-fake bit in )

sim_parport.N.pin-11-in-fake bit in ( OR <newinstname>.pin-11-in-fake bit in )

sim_parport.N.pin-12-in-fake bit in ( OR <newinstname>.pin-12-in-fake bit in )

sim_parport.N.pin-13-in-fake bit in ( OR <newinstname>.pin-13-in-fake bit in )

sim_parport.N.pin-15-in-fake bit in ( OR <newinstname>.pin-15-in-fake bit in )

sim_parport.N.pin-02-in-invert bit out ( OR <newinstname>.pin-02-in-invert bit out )

sim_parport.N.pin-03-in-invert bit out ( OR <newinstname>.pin-03-in-invert bit out )

sim_parport.N.pin-04-in-invert bit out ( OR <newinstname>.pin-04-in-invert bit out )

sim_parport.N.pin-05-in-invert bit out ( OR <newinstname>.pin-05-in-invert bit out )

sim_parport.N.pin-06-in-invert bit out ( OR <newinstname>.pin-06-in-invert bit out )

sim_parport.N.pin-07-in-invert bit out ( OR <newinstname>.pin-07-in-invert bit out )

sim_parport.N.pin-08-in-invert bit out ( OR <newinstname>.pin-08-in-invert bit out )

sim_parport.N.pin-09-in-invert bit out ( OR <newinstname>.pin-09-in-invert bit out )

sim_parport.N.pin-10-in-invert bit out ( OR <newinstname>.pin-10-in-invert bit out )

sim_parport.N.pin-11-in-invert bit out ( OR <newinstname>.pin-11-in-invert bit out )

sim_parport.N.pin-12-in-invert bit out ( OR <newinstname>.pin-12-in-invert bit out )

sim_parport.N.pin-13-in-invert bit out ( OR <newinstname>.pin-13-in-invert bit out )

sim_parport.N.pin-15-in-invert bit out ( OR <newinstname>.pin-15-in-invert bit out )

AUTHOR

Chris Morley

LICENCE

GPL